1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming an isolation region.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for some time, it is one of the most reliable and low cost method for fabricating device isolation regions. However, there are still some drawbacks of the LOCOS. The drawbacks include internal stress generation and bird's beak encroachment. For a high-integrated circuit, the problem of the bird's beak encroachment of the isolation regions especially cannot be avoided, thus isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is also a common conventional method of forming isolation regions. Shallow trench isolation is formed by using anisotropic etching at first to form a trench in the substrate, and then depositing oxide in the trench to form an isolation region having its top surface levels with the substrate surface.
FIGS. 1 through 5 are cross-sectional views showing a conventional method of fabricating a shallow trench isolation. FIG. 6 is a top view of FIG. 5.
In FIG. 1, a pad oxide layer 22 is formed on a substrate 10. A silicon nitride layer 24 is formed on the pad oxide layer 22 by using chemical vapor deposition. A patterned photoresist layer 28 is formed on the silicon nitride layer 24. The patterned photoresist layer 28 is used as a mask to etch the silicon nitride 24, the pad oxide layer 22, and the substrate 10 by using conventional photolithography process. A trench 30 is formed in the substrate 10. The patterned photoresist layer 28 is removed.
In FIG. 2, a thermal oxidation step is performed. A liner oxide layer 31 is formed on the sidewall of the trench 30 and conformal to the trench 30. A tetra-ethyl-ortho-silicon (TEOS) layer 32 is formed over the substrate to fill the trench 30 by using atmosphere-pressure chemical vapor deposition. A densification step is performed to densify the TEOS layer 32 at a temperature of about 1000.degree. C. for 10 to 30 minutes to turn the TEOS layer into a more compact layer.
In FIG. 3, a portion of the TEOS layer 32 on the silicon nitride layer 24 is removed by using chemical mechanical polishing. The silicon nitride layer 24 is used as an etching stop layer. An oxide plug 34 is formed in the trench 30. However, slurry used during the chemical mechanical polishing (CMP) step easily scratches the TEOS layer 32. Therefore, defects and micro-scratches 25 easily occur in the surface of oxide plug 34, when performing the step of chemical mechanical polishing.
In FIG. 4, a hot phosphoric acid is used to remove the silicon nitride layer 24.
In FIG. 5, the pad oxide layer 22 is removed by immersion in a hydrofluoric (HF) acid solution. Since the TEOS layer 34 has a higher etching rate than the pad oxide layer 22, the thickness of oxide plug 34 removed is higher than pad oxide layer 22. Therefore, the top surface of the oxide plug 34 is leveled with the substrate 10 surface. Still, the oxide plug 34 has a lot of defects and micro-scratches 35 in its surface. The top view of the structure described above is shown in FIG. 6. FIGS. 1 through 5 are cross-sectional views of FIG. 6 taken along I--I.
In the conventional process, the defects and micro-scratches 35 generated during the CMP step lead to a kink effect that further causes short circuits or current leakage. If the defects and micro-scratches 35 on the top of the oxide plug 34 connect the neighboring devices, bridging effect or short circuit problems may occur. Therefore, the defects and micro-scratches 35 on the isolation plug 34 seriously reduce the yield.